As integrated circuits are produced with greater and greater levels of circuit density, efficient testing schemes that guarantee very high fault coverage while minimizing test costs and chip area overhead have become essential. However, as the complexity of circuits continues to increase, high fault coverage of several types of fault models becomes more difficult to achieve with traditional testing paradigms. This difficulty arises for several reasons. First, larger integrated circuits have a very high and still increasing logic-to-pin ratio that creates a test data transfer bottleneck at the chip pins. Second, larger circuits require a prohibitively large volume of test data that must be then stored in external testing equipment. Third, applying the test data to a large circuit requires an increasingly long test application time. And fourth, present external testing equipment is unable to test such larger circuits at their speed of operation.
Integrated circuits are presently tested using a number of structured design for testability (DFT) techniques. These techniques rest on the general concept of making all or some state variables (memory elements such as flip-flops and latches) directly controllable and observable. If this can be arranged, a circuit can be treated, as far as testing of combinational faults is concerned, as a combinational or a nearly combinational network. The most-often used DFT methodology is based on scan chains. It assumes that during testing all (or almost all) memory elements are connected into one or more shift registers, as shown in U.S. Pat. No. 4,503,537. A circuit that has been designed for test has two modes of operation: a functional mode and a test, or scan, mode. In the functional mode, the memory elements perform their regular functions. In the scan mode, the memory elements become scan cells that are connected to form a number of shift registers called scan chains. These scan chains are used to shift a set of test patterns into the circuit and to shift out circuit, or test, responses to the test patterns. The test responses are then compared to fault-free responses to determine if the circuit under test (CUT) works properly.
Scan design methodology has gained widespread adoption by virtue of its simple automatic test pattern generation (ATPG) and silicon debugging capabilities. Today, ATPG software tools are so efficient that it is possible to generate test sets (a collection of test patterns) that guarantee almost complete fault coverage of several types of fault models including stuck-at, transition, path delay faults, and bridging faults. Typically, when a particular potential fault in a circuit is targeted by an ATPG tool, only a small number of scan cells, e.g., 2-5%, must be specified to detect the particular fault (deterministically specified cells). The remaining scan cells in the scan chains are filled with random binary values (randomly specified cells). This way the pattern is fully specified, more likely to detect some additional faults, and can be stored on a tester.
FIG. 1 is a block diagram of a conventional system 10 for testing digital circuits with scan chains. External automatic testing equipment (ATE), or tester, 12 applies a set of fully specified test patterns 14 one by one to a CUT 16 in scan mode via scan chains 18 within the circuit. The circuit is then run in functional mode using the test pattern as input, and the test response to the test pattern is stored in the scan chains. With the circuit again in scan mode, the response is then routed to the tester 12, which compares the response with a fault-free reference response 20, also one by one. For large circuits, this approach becomes infeasible because of large test set sizes and long test application times. It has been reported that the volume of test data can exceed one kilobit per single logic gate in a large design. The significant limitation of this approach is that it requires an expensive, memory-intensive tester and a long test time to test a complex circuit.
These limitations of time and storage can be overcome to some extent by adopting a built-in self-test (BIST) framework as shown in FIG. 2. In BIST, additional on-chip circuitry is included to generate test patterns, evaluate test responses, and control the test. For example, a pseudo-random pattern generator 21 is used to generate the test patterns, instead of having deterministic test patterns. Additionally, a multiple input signature register (MISR) 22 is used to generate and store a resulting signature from test responses. In conventional logic BIST, where pseudo-random patterns are used as test patterns, 95-96% coverage of stuck-at faults can be achieved provided that test points are employed to address random-pattern resistant faults. On average, one to two test points may be required for every 1000 gates. In BIST, all responses propagating to observable outputs and the signature register have to be known. Unknown values corrupt the signature and therefore must be bounded by additional test logic. Even though pseudo-random test patterns appear to cover a significant percentage of stuck-at faults, these patterns must be supplemented by deterministic patterns that target the remaining, random pattern resistant faults. One example of where deterministic patterns are desirable is where multiple tristate gates may drive a bus on the circuit under test.
Tristate gates are often part of an integrated circuit that is tested by BIST. A tristate gate is a simple buffer with an enable signal such that it outputs one of three states: high, low, and floating. Some logic circuits have multiple tristate gates coupled to a common output net. These multiple tristate gates need to be managed so they do not cause contention by driving the net with conflicting values. In a first approach, a single tristate gate is enabled at a time so as to avoid bus contention. A second approach enables multiple tristate gates at the same time, where all the enabled tristate gates drive the net with the same value. Because some designers feel the second approach is undesirable, it will not be discussed further.
FIG. 3 illustrates a problem associated with testing tristate gates using scan flops containing pseudo-random values. Three such tristate gates, if simultaneously enabled, could create errors during BIST. In this case, three memory elements 316, 318, 320 in a scan chain, are coupled to the enable inputs 304, 306, 308, on three tristate gates, respectively, 322, 324, and 326. When the enable signal (e.g., 304, 306, . . . , 308) of a tristate gate is activated, the enabled tristate gate drives its input signal (e.g., 310, 312, . . . , 314, respectively) onto the bus 302. The resultant voltage is captured in flip-flop 328. If two tristate gates (e.g., 322, 324) are simultaneously activated, they both drive the bus, possibly, to conflicting voltage levels leaving an unknown resultant voltage captured in flip-flop 328. These unknown results are called X-sources, which are undesirable because the output value is indeterminable. If pseudo-random patterns are used to load the memory elements in the scan chains, there is a high likelihood that double driving of the bus 302 will occur during testing.
FIG. 4 is a prior art design that ensures only a single tristate gate drives the bus 302 at a time. This design 400 inserts logic gates (i.e., 402, 404, 406, 408) into the enable nets. These logic gates guarantee only a single tristate gate is activated at a given time. During logic BIST, the bist_mode signal 410 is activated thereby activating tristate gate 326, and deactivating the other tristate gates 322, 324. Since the bist_mode 410 feeds directly into the OR gate 408, one tristate enable 308 remains activated throughout BIST testing. However, this configuration does not test for a stuck-at-zero fault on each of the AND gates, since the AND gate outputs are never set. Thus, although bus contention is avoided using this method, many tristate gates remain untested.
FIG. 5 is another prior art design used to test tristate gates. The design 500 inserts logic gates into the enable nets of the BIST logic to ensure only one of tristate gates 322, 324, 326 is activated at a time. Although the approach of FIG. 5 provides better coverage than that of FIG. 4, it still suffers from poor fault coverage for any random set of values scanned into the scan flops (i.e., 316, 318, 320).
Using this approach 500, the first tristate gate 322 is enabled for approximately 50% of the random patterns (e.g., 1-0-0, 1-0-1, 1-1-0, and 1-1-1), the second gate 324 is enabled for 25% of the random patterns (e.g., 0-1-0 and 0-1-1), the third tristate gate 326 is enabled for 25% of the random patterns (e.g., 0-0-1 and 0-0-0). Specifically, the first tristate gate 322 is enabled whenever its corresponding scan flop 316 is activated. The second tristate gate 324 is enabled whenever its corresponding scan flop 318 is activated, so long as the first scan flop 316 is deactivated. The third tristate gate 326 is enabled, so long as both the first and second flops (i.e., 316, 318) are deactivated. Using this approach 500, a scan flop (e.g., 318) enables its corresponding tristate gate (e.g., 324), when the scan flop is activated, and all prior scan flops are deactivated (e.g., 0-1-1 and 0-1-1), and the last tristate gate in the series (e.g., 326) is enabled whenever the prior scan flops in the series are not activated (e.g., 0-0-1 and 0-0-0). As this circuit logic is extend to a greater number of tristate gates, there is a reduced likelihood that the last few tristate gates in the series will be enabled. Using this approach, some tristate gates may be tested many times, while others are rarely (or possibly never) tested.
Thus, there is still a need to provide a test circuit that adequately tests tristate gates in a BIST environment.